This invention relates to a first-in-first-out memory, or FIFO memory, which reads out the data in the sequence of being written in.
The FIFO memory is a device for temporarily storing data without disturbing the sequence of arrival of a signal train when the input time of a signal train from outside is different from its processing time. In the conventional FIFO memory, the following two constructions are known.
In the first construction, data circulates along a stack of registers. In this setup, it is possible to maintain a perfect asynchronism between writing and reading. However, in this construction, if the accumulation capacity is increased, the time to go from input to output becomes longer, and a greater number of elements are necessary to make up the structure, so that the storage capacity is rather limited by these factors.
The second construction is intended to realize an FIFO memory by a random access memory (RAM) and control circuit. In this setup, the accumulation capacity can be substantially increased, but it is difficult to maintain a perfect asynchronism between writing and reading. To overcome this difficulty, it is proposed to adjust the access to the RAM by the cascade connection of a plurality of buffer registers to the input and output of a RAM, (see, e.g. U.S. Pat. Nos. 4,616,338 by Andre Helen et al. or 4,415,994). In this construction, data is written into the input buffer. Later, after acknowledging that the RAM is accessible, this data is transferred into a specified address of the RAM from the input buffer. The data is read out from the output buffer. The data of the output buffer is, after acknowledging that the RAM is accessible prior to this reading operation, transferred from the specified address of the RAM into the output buffer. Usually, this operation is done in synchronism with the clock. If access to the RAM for writing and access to the RAM for reading occur simultaneously, the RAM is sequentially accessed according to the determined procedure.
Thus, by installing buffer registers at the input and output of the RAM, if a write request and a read request should occur simultaneously, the access to the internal RAM is adjusted by the control circuit, and the RAM is accessed sequentially, thereby realizing an FIFO memory which appears to act asynchronously as seen from the outside.
Such constructions require plural buffer registers, aside from the RAM main body, and the control of these registers is complicated. Besides, since the time of storing data in buffer register and the time of writing the data in the RAM or reading the data out of the RAM are different, if there is possibility of consecutive write requests and read requests, it is necessary to install write buffer registers or read buffer registers by the number of assumed continuous requests. In this case, more hardware and a more complicated register control than that mentioned above become necessary.